The latest public work adds fair UR5e verification timings, pre-motion VLA integration checks, and a hardened writer-entry boundary with independently inspectable signed records.
Sentinel-EVC connects final-action verification, one-use authorization and inspectable execution. Core research and implementation are substantially complete, with open-source maintenance continuing. The latest update adds incremental rechecking, Launch Gate integration diagnosis and writer-entry hardening.
Recheck what changed. Preserve what still holds.
In the four-candidate UR5e supplement, full-to-incremental median validation ratios are 1.619× and 1.092×, including parent-certificate amortization and issuance costs. The single-candidate cells are slower at 0.749×. Static geometry and technical repeats remain separate from whole-loop throughput.
CPU validation timings include root amortization and issued-certificate cost. Static bare-arm geometry; four candidates are a separately frozen supplement. No whole-loop or hardware throughput claim.
Check the integration that is actually installed.
Launch Gate blocks 10/10 injected configurations in recorded-adapter replay and 6/6 in the separate GPU study. All 13 recorded and seven GPU-derived decision capsules reproduce on CPU, without rerunning model inference.
Independent signed-record adapter replay and fresh GPU studies. Denominators count fault configurations, not tasks. CPU capsule reproduction does not rerun GPU inference. Finite-probe PASS does not establish physical safety or task success.
Keep approval intact through the final handoff.
Concurrent preparation probes reduce invalid downstream dispatches from 40/40 to 0/40. The revised path writes ten approved copies and denies 30 stale entries. Separately, authenticated encrypted CycloneDDS delivers all 70 records in the software loopback experiment.
Recorded-action software writers, real encrypted CycloneDDS loopback between separate processes, followed by local application probes. Entry-preparation comparison is between Sentinel revisions only. Original 0.802 ms timing is not current gateway latency.
